What is the fetch-decode-execute cycle?

Over the past couple of days we’ve been looking at What is Von Neumann Architecture and Von Neumann Architecture and Processors. During our exploration of Von Neumann architecture we mentioned the fetch-decode-execute cycle, which is sometimes referred to simply as the fetch-execute cycle.

Whilst we now understand the role it plays in Von Neumann Architecture, today we’re going to take a closer look at what actually happens in the fetch-decode-execute cycle.

Fetch-Decode-Execute or Fetch-Execute?

An important note on terminology. Both fetch-decode-execute and fetch-execute cycle refer to the same thing and both are acceptable terms of reference within the industry. But, whilst we’re learning, thinking about it as the fetch-decode-execute cycle will help remind you about all the steps in the process so that you don’t miss any out. For the remainder of this blog post, we will refer to the fetch-decode-execute cycle.

The Fetch-Decode-Execute Cycle

As you might have guessed from the name, this isn’t a linear process. It is constantly repeating. In the event that there are no more instructions to fetch, the processor will pause the cycle which will then resume when a new instruction is available. In all likelihood, the computer your using likely only encounters brief moments where this cycle isn’t running. Even when you’re not actively using the computer, background process – for example anti virus, updates, indexing files etc are likely doing something in the background. You can check this out using the Windows Task Manager (CTRL-ALT-DEL and ‘Start Task Manager’) and click on the ‘Processes’ tab. If your CPU’s fans are going full speed, you can be assured there’s plenty going on using the fetch-decode-execute cycle!

Steps of the Fetch-Decode-Execute Cycle

  1. The program counter value – that is holding the memory address for the next instruction to be processed – is copied into the memory address register. Not sure what these are? We introduced them in Von Neumann Architecture and Processors.
  2. The program counter value and memory address register value are now equal. The program counter should always hold the value of the next instruction to be processed so this is incremented so that the value now points to the next instruction to be processed after we’ve completed this iteration of the cycle.
  3. The processor signals the data at the location stored in the memory address register to be retrieved by a bus. Just like registers there are different types of buses. Think of them in the same way as a normal bus, they’re used to get things from A to B (or location to location). The address bus is sent to the memory location stored in the memory address register to pick up the data that it contains.
  4. The value stored at the location the address bus arrives at, whether this be a block of data or an instruction, is collected and is sent using the data bus to the memory data register in the CPU.
  5. Having arrived safely at the CPU, the data stored in the memory address register is transferred (or copied) into the current instruction register.
  6. The value in the current instruction register is then decoded prior to processing and then is executed.
  7. Any intermediate results during processing (execution) are stored in the accumulator.

This cycle continues to repeat until all instructions have been processed. This can generate a lot of heat, which is why your CPU has a fan to keep it cool and ensure that it doesn’t overheat and break whilst it’s really busy!


And that’s it! Nothing more to it. If you’ve read the two articles above (and you should, they’re good!) you now understand What Von Neumann architecture is, the registers that form part of a processor within Von Neumann Architecture and the steps followed in the fetch-decode-execute cycle!

Give yourself a pat on the back and leave any questions or ideas for new posts in the comments below!

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